The data processing technique in which data is sequentially processed by a plurality of serially connected processing stages is known as chain or pipeline processing. This technique allows for a number of different operations or instructions to be executed simultaneously and is therefore quick in many applications.
Pipeline processing has previously been employed in connection with the processing of digital image data for the purpose of analyzing satellite pictures, image enhancement of pictures taken from space probes, etc. In fact, a two dimensional array of synchronized processors has been suggested for use as a pipeline for processing successive images or sections of one image, to achieve increased processing speed. Once each micro-processor performs a computational cycle for the information for one image, it becomes immediately available to perform a computation cycle for information for another image. Additional background information concerning array processing of digital image data may be found in our U.S. Pat. No. 4,215,401, issued July 29, 1980.
Known prior art unit cells employed in pipeline processing systems are limited in the type of data transformations which can economically be performed. A greater number of possible cell operations requires considerably more hardware, thus making complex data transformations particularly costly.
It is therefore a primary object of the present invention to provide a pipeline processing system in which a maximum number of types of data operations may be performed, thereby increasing the number of transformations which can be carried out, while significantly reducing the amount, and therefore cost, of hardware comprising each unit cell.
A further object of the present invention is to provide a processor of the type described above which is significantly faster in operation than systems heretofore employed.
A still further object of the invention is to provide a pipeline processor suitable for performing complex transformations on a data matrix.
Another object of the invention is to provide a unit cell for use in a serial chain thereof forming a pipeline processor which is particularly simple in construction and which is readily adaptable to be embodied in an integrated micro-circuit.
These and further objects of the invention will be made clear or will become apparent during the course of the following description.